Challenges in Low Power Microprocessor Design

This paper addresses the challenge of controlling power dissipation in the microprocessor domain. System level power management architectures [I] have helped control chip-set and peripheral power substantially. But the consequence is that the CPUs are now the power limiters, especially in the mobile domain. This paper addresses two challenges in power reduction of high-performance CPUs. First we indicate areas of maximum impact in power efficient design strategies for high-performance microprocessors. Then we address the issue of power benchmarking in the context of system design and power reduction.